If a PWM power converter uses a non-fixed frequency system architecture, such as a constant on-time or constant off-time control system, the frequency of the PWM power converter may deviate from the designed value under different loading and cause new problems. For example, two channels on a printed circuit board (PCB) are designed to operate with a frequency difference of higher than 100 KHz therebetween, but the real operation frequencies of the two channels may quite close to each other under certain loading, thereby causing audio beating. FIG. 1 is a circuit diagram of the basic architecture for constant on-time and constant off-time PWM, and FIG. 2 is a waveform diagram thereof. Referring to FIGS. 1 and 2, a comparator 10 compares the output voltage Vout of the system with a reference voltage Vref1 to generate a comparison signal S1, and a PWM signal generator 12 generates a PWM signal S2 according to the comparison signal S1 to drive a power output stage 14 to convert an input voltage VIN into the output voltage Vout. In the PWM signal generator 12, responsive to the comparison signal S1, a constant-time trigger 16 triggers a constant on-time Ton or a constant off-time Toff, whose width is set by a current I1 provided by a current generator 18. For example, FIG. 3 is a circuit diagram of the constant-time trigger 16 for constant on-time PWM, in which the comparison signal S1 is used to control a switch SW3 and thereby determine the time point at which a capacitor C1 is to be charged, and a comparator 22 compares the capacitor voltage VC1 with a reference voltage Vref2 to generate the PWM signal S2. Once the comparison signal S1 triggers a flip-flop 20 to turn off the switch SW3, the current I1 charges the capacitor C1 and thereby the capacitor voltage VC1 increases from zero at a constant speed. When the capacitor voltage VC1 becomes as high as the reference voltage Vref2, the PWM signal S2 turns off the on-time Ton. As the current I1 is constant, the on-time Ton of the PWM signal S2 has a fixed width. In the system shown in FIG. 1, error under different loading mainly comes from three sources:
(1) The variation of the phase node voltage Vp (=V−IL×Ron) with the load current IL, where Ron is the on-resistance of the high side power switch SW1;
(2) The voltage drop (IL×RL) caused by the inductor L and the parasitic resistance RL of the PCB; and
(3) The increased frequency caused by the reduced pulse width of the phase node voltage VP resulted from the shorter deadtime time under heavy loading.
Referring to FIGS. 1 and 4, in order to avoid the power switches SW1 and SW2 turning on at the same time, the system usually inserts a preset deadtime before the power switch SW1 turned on. At heavy loading, the duty cycle is very large but the deadtime will reduce the real on-time of the power switch SW1, thereby reducing the pulse width of the phase node voltage VP. As a result, the voltage regulator increases its operating frequency.
U.S. Pat. No. 6,456,050 uses a timing control circuit to generate a timing signal in response to the duty cycle for constant off-time control; however, a fixed frequency is achievable only when the input/output voltage ratio is less than 0.5. U.S. Pat. No. 6,774,611 uses a phase locked loop (PLL) to control the duty cycle of the PWM signal and thus provide precise frequency control, but the circuit is highly complicated.